The need for transistors which can provide high power drive capacity on semiconductor integrated circuits led to the development of lateral double-diffused metal oxide semiconductor (LDMOS) devices. Applications that are particularly significant for LDMOS devices include high and low side drivers for output buffers, radio frequency (RF) circuitry, and the like. Double diffused MOS devices (DMOS) are used for applications where high voltage capacity and low resistance are needed. LDMOS transistors exhibit high breakdown voltage BVdss and low on resistance RDSon, and are therefore well suited to high power applications.
In a transistor formed with a DMOS process, source and backgate diffusions are formed by simultaneous or contemporaneously performed ion implantation into the substrate and subsequent drive anneals. Drain diffusions are spaced from a channel region underlying a gate electrode by a drift region, which can be formed underlying an isolation region. The spacing between the resulting diffusions at the surface of the semiconductor substrate determines the channel length of the LDMOS transistor.
FIG. 1 depicts in a cross sectional view a conventional LDMOS device 100. In FIG. 1, a p-type semiconductor substrate 110 is provided. A p-type epitaxial layer 114 is shown in FIG. 1 formed over the substrate. An N type buried layer labeled “NBL” and numbered 120 is shown at the bottom of the LDMOS structure, NBL 120 is formed by a photomask patterning and ion implantation step. In addition, P type buried regions labeled “PBL” and numbered 116 are shown. These regions are formed with a second separate mask patterning and separate ion implantation step. The LDMOS device 100 includes two symmetric portions on either side of a source region formed in a diffusion DWL 136, each side having a gate and drain arrangement, typically these regions are coupled together to form a large transistor, although alternatively two transistors with a common source and backgate portion can be formed. Many regions similarly formed and arranged may be coupled in common to form still larger transistors.
In FIG. 1, deep N well regions numbered 118 are shown on either side of the EPI region 114. In each of the regions 118, a shallow N well labeled “SNW” and numbered 121 is shown forming drain diffusions. Outside of the deep N-well regions 118, a shallow P-well labeled “SPW” and numbered 122 is shown, working with P-EPI 114 and PBL 116, this forms isolation between the integrated LDMOS device 100 and other nearby device junctions. In each of the regions 118, there is also a P buried layer region numbered 116 on the top of NBL 120 as shown in FIG. 1, forming charge balance between the PBL to DNW regions for a reduced surface field effect (“RESURF”) of the LDMOS device. In an example arrangement the deep N wells 118 can be formed from n-type doped areas, while the shallow N well regions labeled “SNW” numbered 121 can be formed from low voltage CMOS N type diffusion wells used in a semiconductor process for MOS devices. These SNW regions 112 are used for making the LDMOS drain contact to DNW 118 electrical connection. Further, the drain terminals D formed in conductors overlying the substrate can be coupled with drain contact areas 128 can be formed from CMOS source/drain n+ doped diffusions.
In FIG. 1, two gate electrodes numbered 132 are shown overlying the substrate surface. In operation a potential on the gate terminal will turn on the transistors and form a channel region in the substrate where carriers can travel from source to drain. An N+ source region numbered 134 is formed within a p-type D-well diffusion labeled DWL and numbered 136. An additional P+ D-well contact region 135 butting with N+ source 134 is used for D-well connection. Isolation oxide regions 130 which may be formed by shallow trench isolation are shown in FIG. 1 overlying the drift regions and labeled “STI.” The DNW is provided by an ion implant to form a drift region underneath STI, labeled “RESURF” 138, which is used to provide a reduced surface field effect (“RESURF”) for the LDMOS transistor. The RESURF LDMOS transistor has an increased break down voltage BVdss, which is needed for handling the high voltages experienced by power devices.
In operation, electron carriers transit a channel region formed beneath the gate from the source region and then transit the drift region to the drain terminal. In an example application, the source terminal S is coupled to a ground potential while a high voltage, such as 35, 50 or more volts, is coupled to the drain terminal. The potential at the gate terminal 132 can then be used to turn on the device, and the high power current then flows through the device (from drain to source, opposite the electron carrier direction).
In the known approaches to power devices, use of LDMOS transistors is known to provide a device with a high breakdown voltage characteristic capable of handling very high voltages, for example 50 Volts at a source or drain terminal, and having relatively low resistance, Rdson. However, the prior known LDMOS device 100 depicted in FIG. 1 is still subject to various problems and performance issues. Devices that require less silicon area are also needed to increase the integration and to reduce the area of integrated circuits which include the LDMOS transistor. At a targeted high voltage of the LDMOS device, a single RESURF in drift region may be not enough to handle high voltage between the device drain to source at a reduced drift length that occurs as the semiconductor processes continue to shrink. Further, at a smaller drift length, the electric field in the region “X” (JFET area labeled “X” in FIG. 1) becomes stronger, which easily induces a lower device drain to source breakdown voltage and also leads to current crowding in the labeled “X” region, and this may result in a channel hot carrier (“CHC”) effect. In CHC, some carriers (electrons or holes) can tunnel into the gate dielectric, for example, and become trapped, degrading the gate dielectric material, and lowering transistor device performance and reliability. In addition, the use of the buried layers “NBL and “PBL” adds complexity to a standard CMOS semiconductor manufacture process by requiring additional and specific photo-masks, pattern, and implant steps, increasing production costs.
A continuing need thus exists for an LDMOS transistor device with improved reduced surface field effect performance. An LDMOS transistor that is manufacturable alongside standard CMOS devices is needed with reduced process steps and reduced costs when compared to prior known approaches. A need exists for an LDMOS device with very high breakdown voltage BVdss, reduced on-resistance, improved CHC performance, and which require lower silicon area at lower costs than that required for prior known LDMOS devices.